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Senior Verification Methodology Engineer
at AMD (Anywhere)
SCOPE:
As a senior technical member of AMD’s central Verification tools and methodology organization, identify and implement new solutions that improve the quality and Time To Market of all AMD chip designs. Work with project verification teams at AMD design centers worldwide to understand new design features and the resulting verification challenges. Also identify inefficiencies in the IP/SOC verification flow and architect improvements. Tackle cross-discipline methodology challenges such as design methodology for power verification and reset/X simulation at RTL level. Work with Academic and EDA industry leaders to learn, develop and deploy new techniques.
PREFERRED EDUCATION AND EXPERIENCE:
BS + 9 years,, MS + 7 years or PhD + 5 years of experience desired. Requires demonstrated technical proficiency and leadership expertise in cutting edge functional verification methodologies, and their application to the verification of complex microprocessor and/or high performance graphics SOC designs. Experience with Verilog HDL simulation, System Verilog, programming in scripting languages such as Perl or Ruby, and compiled C++ are requirements. Broad understanding of VLSI design, including familiarity with RTL architecture and basic EE principles is a plus. Requires superb communication and leadership skills.
As a senior technical member of AMD’s central Verification tools and methodology organization, identify and implement new solutions that improve the quality and Time To Market of all AMD chip designs. Work with project verification teams at AMD design centers worldwide to understand new design features and the resulting verification challenges. Also identify inefficiencies in the IP/SOC verification flow and architect improvements. Tackle cross-discipline methodology challenges such as design methodology for power verification and reset/X simulation at RTL level. Work with Academic and EDA industry leaders to learn, develop and deploy new techniques.
PREFERRED EDUCATION AND EXPERIENCE:
BS + 9 years,, MS + 7 years or PhD + 5 years of experience desired. Requires demonstrated technical proficiency and leadership expertise in cutting edge functional verification methodologies, and their application to the verification of complex microprocessor and/or high performance graphics SOC designs. Experience with Verilog HDL simulation, System Verilog, programming in scripting languages such as Perl or Ruby, and compiled C++ are requirements. Broad understanding of VLSI design, including familiarity with RTL architecture and basic EE principles is a plus. Requires superb communication and leadership skills.
Published at 08-23-2010
Viewed: 626 times
Viewed: 626 times